轉職熱搜工作

1.開發嵌入式硬體驅動程式及驗證硬體設計 2.維護及開發硬體信任根功能, 包含簽名校驗, 密鑰管理, 版本回滾保護,度量啟動, 權限存取管控 3.整合新產品規格功能

Senior Technical Program Leader | USB3/USB4 Customer Issue Resolution

1.Propose design verification plan and do the execution based on IP and system HW architecture/application 2.Develop design verification environment 3.Develop required verification methodology and adopt into project 4.Develop HW emulator/FPGA platform to accelerate design verification task 5.Co-work with SW/HW engineering to valid function and shift-left SW develop 6.Debug and root cause failure with SW/HW engineering in both pre-silicon and post-silicon

1.RTL platform design integration (clock/reset/power/bus design and architecture, MBIST, etc.) - use for FPGA and Emulator should also be considered 2.Integration quality check (RTL/SDC/Power spec signoff check)

北美電信商晶片認證 1.北美各電信商(ex: AT&T, Verizon, T-mobile) 的晶片認證所需的儀表, 基站, 實網等不同領域的驗證需求. 2.針對不同類型的客戶產品評估需求/風險, 提前規劃預測試協助客戶順利取得北美電信產品認 3.內部多專案與客戶專案並行時, 內部協調測試資源優化各專案進行度並避免客戶緊急問題延燒

1. Optimize 6G/5G modem architecture and associated hardware/software flows in aspects of system performance/power/area (PPA) to improve product competitiveness. 2. Develop architectural simulation, system-level modeling, and analysis platforms for modem baseband system performance, low-power optimization, and hard real-time (HRT) latency analysis. 3. Collaborate closely with domain architects to deliver quantitative reports based on simulation data, driving key architectural decisions. 1. 優化 6G/5G 解調架構及相關的硬體/軟體流程，提升系統效能／功耗／面積（PPA），增強產品競爭力。 2. 開發架構模擬、系統級建模與分析平台，用於評估基帶系統效能、低功耗優化與硬實時（HRT）延遲分析。 3. 與領域架構師緊密合作，根據模擬數據產出量化報告，推動關鍵架構決策。

職責要求 1.執行1.5KW~7.5KW永磁同步馬達（PMSM）及無刷直流馬達（BLDC）的驅動硬體開發，包含功率電子、電源管理、驅動電路設計。 2.熟悉DC-DC、AC-DC電路設計，包括逆變器、功率開關（如 MOSFET、IGBT）的選型與應用確保系統效率與穩定性。 3.熟悉 霍爾感測器、編碼器、電流檢測、溫度監測等感測電路 設計 4.具有電磁干擾分析(EMI)及電磁相容性(EMC)設計與測試經驗 5.跨部門溝通與協作-與企劃、研發及生產團隊緊密合作，進行產品設計、驗證與量產導入 6.會使用 Altium Designer 尤佳 任職資格 學歷與經驗： 1.電機工程、自動化控制、電子工程或相關領域本科以上學歷，碩士以上尤佳 2.3年以上馬達驅動器或電機控制系統開發經驗 分析與測試能力： 1.熟練使用示波器、功率分析儀等測試工具進行調試與性能驗證 2.具備故障排除和系統穩定性測試的經驗 3.撰寫設計驗證報告及可靠度測試計畫 加分條件： 1.具備高速電機（如無人機電機、伺服電機）控制經驗者優先考慮 2.熟悉功能安全標準（如 IEC 61508、IEC62061）者尤佳

我們的使命是協助公司將生成式 AI（Generative AI）有效導入日常工作流程，推動員工提升工作效率與創新能力。 此職位將擔任技術團隊與業務單位之間的橋樑，協助規劃 AI 導入策略、設計賦能活動、推廣最佳實務，並蒐集使用者需求與回饋，持續優化 AI 工具的應用成效。 我們期待對 AI 技術充滿熱情，具備優秀溝通能力與推動能力的人才，一同加速企業 AI 轉型。

• Lead GPU verification efforts across unit, subsystem, and full-chip levels, partnering closely with GPU architects, RTL design leads, performance engineers, modeling teams, and software/firmware teams. • Develop a deep understanding of GPU specifications and microarchitecture, including the 3D graphics pipeline, compute workloads, shader cores, memory hierarchy, cache/coherency, command processing, scheduling, and control subsystems. • Define the overall verification strategy, methodology, test architecture, milestones, and quality metrics for assigned GPU IPs and/or top-level GPU integration. • Drive creation and execution of comprehensive verification plans, ensuring traceability from architectural and RTL specifications through test implementation, functional coverage, assertions, and closure. • Lead development and maintenance of scalable SystemVerilog/UVM verification environments, including reusable agents, BFMs, scoreboards, reference models, checkers, and HW/SW co-simulation infrastructure. • Guide the team in developing directed, constrained-random, stress, error-injection, and scenario-based tests for graphics, compute, memory, and control features. • Drive functional and code coverage closure through rigorous coverage analysis, identification of verification gaps, and creation of targeted tests for corner cases and late-stage bug escapes. • Own regression health for the verification scope: establish regression strategy, monitor quality metrics, prioritize failures, coordinate triage, and drive root-cause resolution with design and architecture teams. • Review verification plans, testbench architecture, test code, coverage models, and debug approaches; provide technical mentorship and guidance to DV engineers. • Partner with performance, architecture, and design teams to develop performance-verification workloads, execute emulation/prototyping runs, analyze bottlenecks, and support performance, power, and area (PPA) optimization. • Drive efficient debug of complex RTL, testbench, firmware, and HW/SW co-simulation failures, clearly communicating root cause, impact, and resolution plans to cross-functional stakeholders. • Collaborate effectively across geographically distributed teams and communicate verification status, risks, and closure plans to project leadership.

• Lead FPGA development activities across functional prototyping, emulation, performance evaluation, and database generation flows. • Work closely with architecture, design, verification, software, firmware, and performance teams to understand system requirements and define FPGA implementation strategy. • Drive FPGA functional flow, including RTL integration, FPGA partitioning, synthesis, place-and-route, timing constraints, timing closure, bitstream generation, bring-up, and debug. • Drive FPGA performance flow to support in-house performance evaluation, workload execution, data collection, profiling, and performance database generation. • Design, implement, integrate, and optimize FPGA logic using Verilog/SystemVerilog/VHDL. • Develop and maintain FPGA prototypes and emulation platforms for system validation, software enablement, firmware development, and hardware/software debug. • Support performance analysis by enabling representative workloads, collecting runtime metrics, identifying bottlenecks, and collaborating with architecture/design teams on improvement opportunities. • Define and improve FPGA methodology, automation, build flows, regression infrastructure, and debug processes for both functional and performance use cases. • Support and integrate interfaces such as PCIe, DDR, AXI, Ethernet, SPI, I2C, UART, and other standard protocols. • Provide technical leadership, mentor engineers, coordinate cross-functional execution, and drive issue resolution across multi-site teams.