轉職熱搜工作

1.操作電腦進行資料的審核、輸入、建檔及校正工作 2.根據廠商之設計圖，修改圖面 會BIM（Building Information Modeling，建築資訊模型） 3.協助主管進行調度工務行程、表單整理、進度跟催或其他交辦等工作 成為夥伴，您可以獲得 1.教育訓練補助 2.績效獎金

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熱愛多變有挑戰性的工作，歡迎有企圖心 喜歡並擅長於人溝通，抗壓性高 協助主管經營企業客戶 ※無不良嗜好 ※須懂基本文書作業EXCEL & PPT ※會騎機車佳 ※略懂繪圖軟體AI佳 公司制度： 勞保、健保、員工在職教育訓練、良好升遷制度、週休二日 獎金福利： 年終獎金、三節獎金、禮品、激勵獎金、績效獎金 休假福利： 陪產假、育嬰假、生理假、年假、旅遊假、到職滿半年享特休 保險福利： 員工團保、勞退提撥金 設備福利： 哺乳室 娛樂福利： 國內旅遊、國外旅遊、員工定期聚餐、尾牙、下午茶 補助福利： 員工購物優惠、國內、外旅遊補助

1.操作電腦進行資料的審核、輸入、建檔及校正工作 2.根據廠商之設計圖，繪製施工圖並註明材料規格、位置、尺度及數量等 3.協助主管進行調度工務行程、表單整理、進度跟催或其他交辦等工作 成為夥伴，您可以獲得 1.教育訓練補助 2.績效獎金 歡迎 所有求職者 應屆畢業生

公司期待透過完善的專案歷練與海外跨國舞台，使同仁能獨立操作大型專案，未來逐步晉升為資深系統工程師、系統工程師主管職、部門主管及海外專案核心幹部。 【團隊成長與多元學習福利】 ★ 跨領域成長：我們非常注重團隊發展，提供多元化的學習環境，不侷限於單一技術的學習，讓您的職涯更具廣度與深度！ ★ 證照與進修：公司大力鼓勵每位員工在職進修，全力支持您考取相關專業技術證照，並提供實質的升遷與職涯加分。 ★ 國際化舞台：具備完善的海外發展機制，若工作表現優異，未來將有機會外派至國外工作、參與跨國專案，大幅拓展您的國際視野！ ★ 我們非常期望認真、負責、樂於學習且勇於挑戰自我的人才加入團隊，與公司一同並肩成長！ 本職務為公司工程技術與專案管理之中堅骨幹。透過一線實務的主導、專案進度的精準控管以及跨領域技術的整合，負責帶領工程團隊並指導助理工程師，確保各項專案在品質、安全與時程上完美達標，相關經驗兩年以上。 【日常工作職掌】 專案進度與現場管理 工程技術與圖面作業 設備組裝與安裝測試 行政庶務與工安推行 工安政策與出差配合 ＞＞＞專案出差支援：依專案地點配合出差與合宜之調配安排（需不定期支援台南與高雄廠區往返，或依專案需求配合跨區廠區支援）。

職責要求 •Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks. •Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops. •Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY). •SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits. •Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements. •Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications. •Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off. •Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics. •Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects. •Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control. •Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging). •Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed. •Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams. 任職資格 •BS or MS in Electrical/Electronics Engineering or related field. •Typically 5+ years of relevant experience in analog/mixed-signal IC design, with emphasis on high-speed I/O or memory interface circuits. •Strong fundamentals in CMOS device operation, analog circuit design, feedback and stability, noise/jitter analysis, and deep-submicron effects. •Hands-on experience designing high-speed TX/RX buffers, termination and impedance calibration circuits, and voltage-domain level shifters. •Proficiency with industry-standard design tools, typically including Cadence Virtuoso, Spectre/ADE or HSPICE, and post-layout extraction flows. •Ability to clearly communicate design intent, document trade-offs, and drive results in a cross-functional environment. •Basic written English proficiency required. Candidates must be able to read and write emails in simple English to communicate effectively with non-Mandarin-speaking colleagues. Preferred / Nice-to-Have Experience •Experience with memory or high-speed interface protocols such as LPDDR, DDR, HBM, or similar interfaces. •Experience with post-layout sign-off, EM/IR analysis, and reliability-aware analog design. •Familiarity with signal integrity concepts, channel effects, and interaction between I/O circuits and package/channel parasitics. •Experience supporting silicon validation, ATE characterization, and simulation-to-silicon correlation. •Scripting or automation experience using Python, SKILL, Verilog-A, or similar for simulation regression and result analysis.

1.操作電腦進行資料的審核、輸入、建檔及校正工作 2.根據廠商之設計圖，繪製施工圖並註明材料規格、位置、尺度及數量等 3.協助主管進行調度工務行程、表單整理、進度跟催或其他交辦等工作 歡迎 所有求職者 日間就學中 夜間就學中 …等

主要為發電機併聯控制盤、水情收集盤 誠徵 : 電機工程師 / 儲備幹部 1.控制盤規劃與設計Cad繪圖 2.PLC程式及人機程式撰寫 3.從事控制盤之功能廠驗測試 4.從事現場併聯控制盤與發電機控制迴路的連接與測試 5.配合發電機人員做併聯測試 6.從事控制盤之維修、售服 7.高低壓配電盤設計