轉職熱搜工作

Key qualifications: 1. Master degree or above with EE or CS background 2. Familiar with SystemVerilog and Verilog 3. Exposure to OVM/UVM/VMM methodology 4. Exposure to constrained-random based verification environment 5. Exposure to create coverage model and drive coverage closure in including code/functional coverage. 6. Be able to develop a test bench from scratch Preferred qualifications: 1. Familiar with PCI/USB/SATA/Serdes 2. Familiar with Bluetooth 3. Familiar with SOC bus fabric and AXI/AHB/OCP bus protocols 4. Familiar DDR2/3/4 5. Familiar with any type of flash memory 6. Familiar SVA 7. Familiar Formal verification methodology 8. Experience of writing bootloader for ARM/MIPS CPUs 9. Perl/Python experience Job descriptions: 1. Test plan creation 2. Develop testbench, test cases, reference model, coverage model and regression suite 3. Run RTL and gate level simulation, debug failures, manage bug tracking 4. Drive and achieve coverage closure (MD17C0031)

Key qualifications: 1. MS degree or above with EE or CS background 2. Familiar with SystemVerilog and Verilog 3. Exposure to OVM/UVM/VMM methodology 4. Exposure to constrained-random based verification environment 5. Exposure to create coverage model and drive coverage closure in including code/functional coverage. 6. Be able to develop a test bench from scratch 7. Hands on working experience on unit/block/full-chip level verification 8. Good communication skill 9. Leadership/management experience is a plus. Job descriptions: 1. Plan the verification strategy for SOC projects 2. Hands-on verification task of some of the units 3. Work closely with the design teams. 4. Drive the verification team, problem-solving on day-to-day works 5. Provide the measurable metrics for project leads and upper management. 6. Bug/coverage trend identification. Foresee the possible issues and plan for them. (MD17C0031)

工作項目： Digital design verification, including direct test simulation, random test simulation and coverage report. 應徵條件： 1. 學士以上; 電機工程、電控工程、電子工程、資訊工程、資訊科學相關科系畢業為主。 2. 具3年以上數位設計、驗證或 CAD 相關經驗者為佳。

工作項目： 1. 建立IC設計後段驗證流程，並撰寫自動化程式。 2. 建立並維護DRC/LVS/SVS/LVL/ERC/PERC相關檔案及流程。 3. 分析並解決PV相關問題。 應徵條件： 1. 碩士以上；電機、電機與控制、電信、電子、資工、資訊相關科系畢業為佳。 2. 無經驗可；具相關工作經驗者佳。 3. 熟悉 Linux工作環境以及 TCL/shell script. 4. 熟悉 Calibre(含TVF及SVRF)或 ICV. 5. 熟悉 FinFET或 BCD製程為佳。

工作項目： Verification for High Speed PHY projects, which includes: 1. Responsibility for test plans, testbench documentation and implementation. 2. Use SystemVerilog language, SVA and UVM methodology for block level verification. 3. Debug tests with design engineers to deliver functionally correct design blocks. 4. Close coverage measures to identify verification holes and show progress towards tape-out. 5. Write scripts to automate routine parts of verification workflow. 應徵條件： 1. 碩士以上; 電子、電機、資工、電信、電控、資科等相關科系畢業為主。 2. 具0~3年下列經驗之一者尤佳： (1) Experience verifying digital logic at RTL using SystemVerilog for FPGAs and/or ASICs. (2) Experience verifying digital systems using standard IP components/interconnects. (3) Experience creating and using verification components and environments in standard verification methodology. 3. Preferred qualifications: (1) Experience with high speed MAC/PHY RTL design or verification. (2) Experience with UVM methodology and coding. (3) Good English verbal communication skills.

工作項目： 1. High-Performance CPU/GPU Timing & Power Integrity Signoff 2. High-Performance CPU/GPU Post-Silicon Validation & Debug, Sim-to-Silicon Correlation 3. 協同開發 CPU/GPU Advanced DFT, On-Chip PVT Sensor, Performance Improvement & Power Management 等先進技術 4. 支援產品 SoC Projects，協同執行 High-Performance CPU/GPU 專案開發，導入先進 IP 及技術 應徵條件： 1. 碩士以上；電機、資工、電子相關科系畢業為主。 2. 熟悉 SoC Integration & Design Flow、Frontend/Backend/DFT/Timing/IR Drop/Power Analysis EDA Tools。 3. 有 ARM Cortex-A CPU/Subsystem Design/Integration/PPA Optimization/Sign-off 經驗尤佳。 4. 有 Chip-Level, Package & PCB Power Integrity Optimization 經驗尤佳。 5. 有On-Chip PVT Sensor 開發經驗尤佳。 6. 有Post-Silicon Validation, Debug 及 RMA 分析經驗尤佳。 7. 積極負責、溝通協調能力強、勇於迎接挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。

工作項目： 1. 開發維護 in-house VIP 2. 支援產品線 IC 驗證計劃 工作地點：台南科學園區 應徵條件： 1. 大學、碩士以上；電機、電機與控制、資訊科學、自動控制、通訊工程、電信、資訊工程、電子、動力機械相關科系畢業為主。 2. 熟悉 SystemVerilog 驗證語言和 perl 相關 scripts。 3. 熟悉 UVM 或 VMM methodology 。 4. 熟悉 PCIE/USB/SATA 等 protocol 。 5. 具4年以上 IC 驗證相關經驗。 6. 有 VIP 開發經驗者尤佳。

1. Summary Realtek Semiconductor Corp., located in the Hsinchu Science-based Industrial Park, Taiwan‘s 〝Silicon Valley〝, established in 1987. Realtek‘s efforts to provide the ultimate in pioneering IC technology — along with its firm commitment to creating unique and innovative designs for a broad range of high-tech applications — have won the company a worldwide reputation and made possible a favorable and consistent growth rate in the years since its establishment. In line with the Realtek culture of 〝Self-confidence and trust in people〝, we believe that we can achieve our best, and trust our colleagues can also do the same. Working and learning in Realtek, we openly share knowledge and experience with one another to inspire innovation and pursue growth of the company, as well the individuals. Talent is the important capital of Realtek. Welcome to Join Realtek Family! 2. Essential Job Functions ‧Locate in Southern part of Germany (Frankfurt to Stuttgart, or Stuttgart to Munich) ‧Provide pre-sales and post-sales support. ‧Understand customer requirements, and deliver technical presentations, reports, documents and technology demonstrations. ‧Support customer product development and design. ‧Support customer issue analysis and resolve. ‧On-site support for debug or certification test. ‧Cross-functional collaboration with Realtek internal resources. 3. Education, Skills, Abilities, And Experience Required ‧M.S. or B.S. in Engineering or equivalent. ‧3 to 5 years of progressive professional technical experience in IC design or related areas, direct experience in IC design house FAE is preferred. ‧Strong analytical and problem solving skills. ‧Strong written/verbal communication and negotiation skills. ‧Being proactive and willing to take initiatives. ‧Ability to work independently to achieve goals. ‧Ability to understand and explain technical issues and solutions to technical and non-technical personnel. ‧Native German skill. ‧Medium or higher English skill. ‧Familiar with Ethernet protocols will be a plus. ‧Familiar with Automotive ecosystem will be a plus. ‧Basic or higher Chinese skill will be a plus. ‧Experience of Linux system will be a plus. 4. Industry Automotive Ethernet, Semiconductor 5. Employment Type Full-time 6. Job Functions Engineering, Business Development

Verification for microprocessor designs. Desired skills and experience includes: 1. Experience in processor design verification: test planning, testbench development, and documentation 2. Knowledge of assembly language, C/C++ and/or SystemVerilog 3. Knowledge of SVA or UVM methodology for block and top level verification 4. Formal property checking/formal verification methodologies 5. Proficiency in scripting languages such as Python/Perl

工作項目： Verification for High Speed PHY projects, which includes: 1. Responsibility for test plans, testbench documentation and implementation. 2. Use SystemVerilog language, SVA and UVM methodology for block level verification. 3. Debug tests with design engineers to deliver functionally correct design blocks. 4. Close coverage measures to identify verification holes and show progress towards tape-out. 5. Write scripts to automate routine parts of verification workflow.